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	<title>Comments on: DSMC ASIC Vs. RED One FPGA</title>
	<atom:link href="http://camerarentalz.com/dsmc-asic-vs-fpga/feed/" rel="self" type="application/rss+xml" />
	<link>http://camerarentalz.com</link>
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		<title>By: david</title>
		<link>http://camerarentalz.com/dsmc-asic-vs-fpga/comment-page-1/#comment-32722</link>
		<dc:creator>david</dc:creator>
		<pubDate>Tue, 18 Jan 2011 10:28:46 +0000</pubDate>
		<guid isPermaLink="false">http://camerarentalz.com/?p=1526#comment-32722</guid>
		<description>ASICs are fabricated using a photolithographic process, bottom up, starting from the basic components transistors and finishing up with the metal layers which connect the processors, power supplies etc.

A complex ASIC can require 40 days to make its way through the fabrication process, roughly 1 day per processing step, where each mask (Red say they have 27) may require more than one processing step.

In order to save time with prototype devices (not require in mass-production) some wafers can be held in the wafer fab at the later stages of upper metal layer processing.

The advantage is that instead of taking 40+ days to fix a bug it takes only a few weeks, assuming the problem can be fixed using only changes to metal layers, a &quot;metal spin&quot;.</description>
		<content:encoded><![CDATA[<p>ASICs are fabricated using a photolithographic process, bottom up, starting from the basic components transistors and finishing up with the metal layers which connect the processors, power supplies etc.</p>
<p>A complex ASIC can require 40 days to make its way through the fabrication process, roughly 1 day per processing step, where each mask (Red say they have 27) may require more than one processing step.</p>
<p>In order to save time with prototype devices (not require in mass-production) some wafers can be held in the wafer fab at the later stages of upper metal layer processing.</p>
<p>The advantage is that instead of taking 40+ days to fix a bug it takes only a few weeks, assuming the problem can be fixed using only changes to metal layers, a &#8220;metal spin&#8221;.</p>
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		<title>By: ben weinstein</title>
		<link>http://camerarentalz.com/dsmc-asic-vs-fpga/comment-page-1/#comment-2305</link>
		<dc:creator>ben weinstein</dc:creator>
		<pubDate>Mon, 18 Jan 2010 09:24:17 +0000</pubDate>
		<guid isPermaLink="false">http://camerarentalz.com/?p=1526#comment-2305</guid>
		<description>now were talking!  smaller, cooler, faster. do it!</description>
		<content:encoded><![CDATA[<p>now were talking!  smaller, cooler, faster. do it!</p>
]]></content:encoded>
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	<item>
		<title>By: Nelson</title>
		<link>http://camerarentalz.com/dsmc-asic-vs-fpga/comment-page-1/#comment-2069</link>
		<dc:creator>Nelson</dc:creator>
		<pubDate>Fri, 25 Dec 2009 03:28:44 +0000</pubDate>
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		<description>But where does &#039;spin&#039; or &#039;metal spin&#039; fit in?  I thought ICs were all photographic or photolithographic processes.</description>
		<content:encoded><![CDATA[<p>But where does &#8216;spin&#8217; or &#8216;metal spin&#8217; fit in?  I thought ICs were all photographic or photolithographic processes.</p>
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	<item>
		<title>By: Travis Freeburg</title>
		<link>http://camerarentalz.com/dsmc-asic-vs-fpga/comment-page-1/#comment-1863</link>
		<dc:creator>Travis Freeburg</dc:creator>
		<pubDate>Tue, 01 Dec 2009 06:49:43 +0000</pubDate>
		<guid isPermaLink="false">http://camerarentalz.com/?p=1526#comment-1863</guid>
		<description>Thanks! i was wondering... and u guys explained.</description>
		<content:encoded><![CDATA[<p>Thanks! i was wondering&#8230; and u guys explained.</p>
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